Engineering ePoP Memory for Space-Constrained Devices: Why LPDDR5X and eMMC 5.1 Integration Matters

As mobile and wearable devices become thinner while their computing capabilities continue to increase, memory architecture is becoming an increasingly important part of system design. The challenge is no longer simply how to provide sufficient DRAM capacity or storage. Designers must also consider PCB area, package height, signal integrity, power distribution, thermal conditions, and long-term storage reliability within an increasingly constrained mechanical envelope.

This is where embedded Package-on-Package (ePoP) technology becomes particularly relevant. By vertically integrating different memory technologies into a single package, ePoP can move part of the optimization challenge from the board level to the package level.

A current example is BIWIN’s 201-ball ePoP5X, which combines LPDDR5X DRAM with eMMC 5.1 storage in an 8.00 × 9.50 mm package. The solution is designed for high-end smart wearables, mobile devices, and other applications where space and memory performance must be balanced.

The Memory Architecture Challenge in Compact Devices

For a conventional computing platform, DRAM and non-volatile storage can be implemented as separate components. This provides flexibility during board design, but it also consumes additional PCB area and requires designers to accommodate separate component footprints, routing requirements, power domains, and signal paths.

The constraints become more significant in products such as smartwatches, AI-enabled wearables, AR/VR devices, and compact mobile modules. These products have limited internal volume, while their workloads increasingly involve multimedia processing, wireless connectivity, local applications, and AI-related functions.

Consequently, memory architecture has to be considered together with the mechanical and electrical design of the system.

A package-level integration approach can address part of this challenge by combining memory functions into a vertically stacked structure. Instead of allocating separate PCB areas to DRAM and embedded storage, an ePoP solution can integrate these components into a single package footprint.

Why Integrate LPDDR5X and Embedded Storage?

LPDDR5X and embedded storage perform fundamentally different functions within a system.

LPDDR5X serves as high-speed working memory for the processor. It provides the bandwidth required for active workloads such as application processing, graphics, multimedia, and AI-related tasks.

Embedded storage, on the other hand, provides persistent data storage for the operating system, applications, user data, and other content that must remain available when the device is powered off.

Integrating these two technologies does not make them interchangeable. Instead, the value lies in placing two complementary memory functions within a highly integrated package architecture.

BIWIN’s ePoP5X combines LPDDR5X memory with eMMC 5.1 storage and supports memory data rates of up to 8533 Mbps. Its eMMC component provides sequential read speeds of up to 300 MB/s and sequential write speeds of up to 150 MB/s.

This distinction is important when evaluating specifications. DRAM data rate and storage throughput represent different aspects of system performance and should not be directly compared as if they were equivalent metrics.

Why the 201-Ball Package Matters

As LPDDR memory data rates increase, package design becomes increasingly important.

Higher-speed memory interfaces place greater demands on signal routing, power delivery, grounding, and overall signal integrity. A package must therefore accommodate not only the physical connection between the memory devices and the host system, but also the electrical requirements of higher-speed operation.

The ePoP5X uses a 201-ball configuration specifically designed for LPDDR5X-based ePoP applications. According to BIWIN, the higher pin count supports the increased signal, power, and ground requirements associated with faster data rates.

The package has an 8.00 × 9.50 mm footprint and a thickness of ~0.54 mm. That enables the LPDDR5X and storage elements to be stacked in a small vertical package, enabling a smaller PCB area for the memory subsystem.

This is not just about higher-density connectivity; the 201-ball design was created with several factors in mind. It is a key part of the electrical and mechanical design, enabling higher-speed memory in a compact form.

Package Density: More Memory Function in Less Board Area

One of the obvious benefits of ePoP is a reduction in PCB footprint, but it isn’t just about making a component smaller.

BIWIN’s ePoP5X uses multi-layer die stacking, ultra-thin dies, and heterogeneous multi-chip integration to integrate LPDDR5X and embedded storage in an 8.00 x 9.50 mm package. The resulting thickness of the package is about 0.54 mm.

This allows more memory to fit within a safe package envelope.

The benefits for device designers are not confined to saving board space. Fewer memory subsystem components allow greater flexibility in deploying batteries, sensors, processors, wireless components, and other components.

This is especially important in wearable devices where PCBs are limited by the area of the PCB and size of the housing.

Performance Must Be Evaluated at the Architecture Level

Peak specifications are useful, but they do not tell the entire story.

LPDDR5X part of the ePoP5X features data rates up to 8533 Mbps, whereas the eMMC 5.1 part supports up to 300 MB/s sequential read and up to 150 MB/s sequential write performance.

These numbers refer to various levels of the memory architecture.

LPDDR5X interface is aimed at high-speed transfer of temporary data between the processor and working memory. The eMMC is used for persistent memory and has its own controller and storage management system.

For system designers, the question is instead: which has the higher numerical throughput, and how relevant is that to them? Instead, it is more important to determine whether the overall architecture provides sufficient bandwidth for working memory, high performance for persistent storage, physical compactness, and low power usage.

Reliability Becomes More Important as Integration Increases

Compact packaging doesn’t replace data reliability and storage management. But the highly integrated memory solutions need to solve NAND-related issues in a compact footprint.

The ePoP5X packs global wear leveling management and LDPC error correction. It is also capable of supporting firmware field updates (FFU) as well as storage-management features such as garbage collection, TRIM, write protection, and quick erase.

Wear leveling spreads write operations across the NAND storage area instead of repeatedly writing to the same physical blocks. LDPC error correction technology detects and corrects certain types of NAND-related errors, enhancing data integrity throughout the product’s life.

The following functions show that embedded storage is not just measured by capacity and sequential speed. All of these factors are part of the storage architecture.

Power and Thermal Constraints in Thin Devices

Memory integration also affects power and thermal design.

The eMMC part of the ePoP5X runs at 3.3 V and 1.8 V power domains for the memory, and the LPDDR5X part has lower-voltage memory power domains. The temperature range is -25°C to +85°C.

These are important qualities for small equipment because there is less physical space to dissipate heat or to house power management components.

While a highly integrated memory package can reduce board-level placement complexity, system designers must consider power consumption, thermal characteristics, system workload, and enclosure design when evaluating the entire system.

This is especially true of battery-powered wearables, where memory is a need that has to be weighed against the power budget.

Where ePoP Architecture Makes the Most Sense

The advantages of this architecture are particularly relevant to products where physical size and memory requirements are both important.

Smart Wearables

The PCB space and volume of smartwatches and other wearable devices are small. Meanwhile, they also need more local storage, more bandwidth and more powerful processors.

memory subsystem can be shrunk by integrating LPDDR5X and an embedded-storage package into the same package, providing more board space for other components.

AR and VR Devices

AR and VR products not only can demand high-speed memory for graphics, sensor processing, and real-time workloads, but also require local storage for applications and content.

Incorporation of high-speed LPDDR5X memory and onboard storage in a small form factor can meet these requirements in space-sensitive applications.

Mobile Modules

Compact memory architecture is another advantage of mobile computing platforms. The ePoP5X is intended for a wide range of applications, from mobile devices to modules, where space and memory constraints can significantly impact system design.

A Practical Example: BIWIN ePoP5X

BIWIN’s 201-ball ePoP5X illustrates how these engineering requirements can be addressed within a single memory package.

Its key specifications include:

According to BIWIN, the ePoP5X is able to raise the frequency of memory by 128.6% compared to its predecessor and reduces the package size by 32%. The product is also officially certified on Qualcomm’s 6100 platform.

LPDDR5X and eMMC 5.1 integrate to offer a strong balance of working-memory performance and persistent-memory data retention, alongside package-level space efficiency for engineers considering integrated memory architectures.

Conclusion

In today’s mobile and wearable systems, where system components are shrinking while computing demands grow, memory architecture has shifted from a part-selection decision to a system-level design decision.

One of the methods that ePoP technology offers is to shift memory integration from the PCB off-chip to the package. Using LPDDR5X and embedded storage together enables designers to tackle working-memory bandwidth and persistent storage in a small mechanical package.

Meanwhile, high peak performance is not enough for successful implementation. The effectiveness of an integrated memory solution includes pin configuration, signal integrity, power and ground distribution, package density, thermal behavior, NAND management, and firmware capabilities.

With memory performance and package integration, this is a package worthy of consideration for space-constrained applications like smart wearables, AR/VR, and mobile products for the next generation of compact electronics.